• 可以添加代码列表，编辑公式，文档包含首页，目录，页眉页脚，参考文献以及目录自动索引等。
• 使用xeCJK中文环境，采用了Adobe的几套字体，大家可以从网上下载相关字体，或修改为自己PC机上有的字体。
• 在CTEX2.9下采用XeLaTeX+MakeIndex+BibTeX编译无错，我保留了内容，为了方便查看效果，修改相应部分即可。
• 先来看看整体排版效果如何：

• LaTeX源代码如下：

\documentclass[10pt]{article}\usepackage[CJKchecksingle,CJKnumber]{xeCJK}\setCJKmainfont[BoldFont={Adobe Heiti Std},	ItalicFont={Adobe Kaiti Std}]{Adobe Song Std}\setCJKsansfont{Adobe Heiti Std}\setCJKmonofont{Adobe Fangsong Std}\punctstyle{hangmobanjiao}\usepackage{graphicx}\usepackage{fancyhdr}\usepackage{amsfonts}\usepackage{booktabs}\usepackage{listings}\lstset{numbers=left,numberstyle=\tiny,keywordstyle=\color{blue!70}, commentstyle=\color{red!50!green!50!blue!50},frame=shadowbox,basicstyle=\ttfamily\tiny,rulesepcolor=\color{red!20!green!20!blue!20}}\usepackage[svgnames, table]{xcolor}\usepackage[bookmarksnumbered, pdfencoding=auto, pdfpagelayout=TwoPageRight,breaklinks, colorlinks, linkcolor=blue, urlcolor=blue]{hyperref}\usepackage{subfig}\newcommand{\Original}{\fontsize{38pt}{\baselineskip}\selectfont}\renewcommand{\contentsname}{目录}\renewcommand{\figurename}{图}\renewcommand{\refname}{参考文献}\renewcommand{\figureautorefname}{图}\pagestyle{fancy}\begin{document}\begin{titlepage}\center{\Original{数字系统EDA技术}\\\Original{实验报告}}\vspace{5cm}\begin{center}\begin{large}\begin{tabular}{cc}实验名称:& 序列发生器和检测器的设计\\\cline{2-2}\\指导老师:& X~X~X\\\cline{2-2}\\学生姓名:& X~X~X\\\cline{2-2}\\学\qquad 号:&2010021XXXXXXX\\\cline{2-2}\end{tabular}\end{large}\end{center}\vfill \hfill  \emph{\today}\end{titlepage}\newpage看不清楚的地方请放大后查看，谢谢！\tableofcontents\newpage\section{实验名称:序列发生器和检测器的设计}\section{实验要求}\begin{enumerate}\item[1.]连续完成一个“10001110”序列和九个非“10001110”序列的发生；\item[2.]检测“10001110”序列，当检测到该序列后点亮EDA实验箱的LED灯；\item[3.]注意为了点亮LED灯，时钟频率不要选择太高，可以选择几十赫兹的频率。\end{enumerate}\section{实验目的}\begin{enumerate}\item[1.]掌握序列发生器和检测器的工作原理；\item[2.]学会用状态机进行数字系统设计。\end{enumerate}\section{实验器材}\begin{itemize}\item PC机一台\item EDA教学实验系统一台\item 下载电缆一根（已接好）\item 导线若干\end{itemize}\section{\textbf{实验原理}}\subsection{\textbf{序列发生器原理}}在数字信号的传输和数字系统的测试中，有时需要用到一组特定的串行数字信号，产生序列信号的电路称为序列信号发生器。本实验要求产生一串序列“10001110”。该电路可由计数器与数据选择器构成，其结构图如下，其中的锁存输出的功能是为了消除序列产生时可能出现的毛刺现象：\begin{figure}[htbp]\centering\includegraphics[scale=0.6]{princ1.eps}\caption{\small{序列发生器框图}}\end{figure}\subsection{\textbf{序列检测器的基本工作过程}}序列检测器用于检测一组或多组由二进制码组成的脉冲序列信号，在数字通信中有着广泛的应用。当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。方框图如下：\begin{figure}[htbp]\centering\includegraphics[scale=0.6]{princ2.eps}\caption{\small{序列检测器框图}}\end{figure}\subsection{\textbf{状态机的基本设计思想}}在状态连续变化的数字系统设计中，采用状态机的设计思想有利于提高设计效率，增加程序的可读性，减少错误的发生几率。同时，状态机的设计方法也是数字系统中一种最常用的设计方法。一般来说，标准状态机可以分为摩尔（Moore）机和米立（Mealy）机两种。在摩尔机中，其输出仅仅是当前状态值的函数，并且仅在时钟上升沿到来时才发生变化。米立机的输出则是当前状态值、当前输出值和当前输入值的函数。本实验要从一串二进制码中检测出一个已预置的8位二进制码10001110，每增加一位二进制码相当于增加一个状态，再加上一个初始态，用9个状态可以实现。其过程如下：\begin{figure}[htbp]\centering\includegraphics[scale=0.6]{princ3.eps}\caption{\small{状态图}}\end{figure}\section{\textbf{实验步骤}}\subsection[\textbf{序列发生器实现}]{\textbf{按照实验要求编写“10001110”序列发生器的程序；}}序列生成器实现，连续产生"10001110"序列和9个非"10001110"序列：50\%：\newline\begin{lstlisting}[language=VHDL]--generate "10001110" and 9 other sequenceslibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned;entity seqgen is	port(clkin:in std_logic;	       clr:in std_logic;	       sqn:out std_logic);end seqgen;architecture behav of seqgen is	signal cnt:integer range 79 downto 0;	signal tmp:std_logic;	signal datatmp:std_logic_vector(79 downto 0);begin	datatmp(7 downto 0)<="10101010";	datatmp(15 downto 8)<="10101010";	datatmp(23 downto 16)<="10101010";	datatmp(31 downto 24)<="10101010";	datatmp(39 downto 32)<="01110001";	datatmp(47 downto 40)<="01010101";	datatmp(55 downto 48)<="01010101";	datatmp(63 downto 56)<="01010101";	datatmp(71 downto 64)<="01010101";	datatmp(79 downto 72)<="01010101";	process(clkin,clr)	begin		if clr = '1' then 			cnt <= 0;		else			if clkin'event and clkin = '1' then				if cnt = 79 then					cnt <= 0;				else					cnt <= cnt + 1;				end if;			end if;		end if;	end process;	process(cnt)	begin		if clkin'event and clkin = '1' then 			tmp <= datatmp(cnt);		end if;	end process;	--output	sqn<=tmp;end behav;\end{lstlisting}序列检测器，包含两个结构体，其中behav\_b更简洁，采用它进行综合：\begin{lstlisting}[language=VHDL]--detect target sequence.library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity sqndtc is	port(clkin:in std_logic;		   clr:in std_logic;		   din:in std_logic;		   dset:in std_logic_vector(7 downto 0);			led:out std_logic;		     d:out std_logic_vector(31 downto 0));end sqndtc;architecture behav_a of sqndtc is	signal q:integer range 8 downto 0;begin	process(clkin,clr)	begin		if clr = '1' then 			q <= 0;		elsif clkin'event and clkin = '1' then 			case q is 				when 0 => if din = dset(7) then q <= 1;						  else q <= 0;end if;				when 1 => if din = dset(6) then q <= 2;						  else q <= 0;end if;				when 2 => if din = dset(5) then q <= 3;						  else q <= 0;end if;				when 3 => if din = dset(4) then q <= 4;						  else q <= 0;end if;				when 4 => if din = dset(3) then q <= 5;						  else q <= 0;end if;				when 5 => if din = dset(2) then q <= 6;						  else q <= 0;end if;				when 6 => if din = dset(1) then q <= 7;						  else q <= 0;end if;				when 7 => if din = dset(0) then q <= 8;						  else q <= 0;end if;				when others => q <= 0;			end case;		end if;	end process;	process(q)	begin		if q = 8 then led <= '1';		else led <= '0';		end if;	end process;end behav_a;architecture behav_b of sqndtc is 	signal reg:std_logic_vector(7 downto 0);	signal dtmp:std_logic_vector(31 downto 0);begin	process(clkin,clr)	begin		if clr = '1' then 			reg <= "00000000";		elsif clkin'event and clkin = '1' then 			reg(7 downto 1) <= reg(6 downto 0);			reg(0) <= din;		end if;		if reg = dset then 			led <= '1';		else			led <= '0';		end if;	end process;	process(clkin,clr)	begin		if clr='1' then 			dtmp <= conv_std_logic_vector(0,32);		elsif clkin'event and clkin = '1' then			dtmp(31 downto 4) <=dtmp(27 downto 0);			dtmp(3 downto 0) <=conv_std_logic_vector(din,4);		end if;		end process;	d<=dtmp;end behav_b;--use behav_b for synthesisconfiguration config of sqndtc is	for behav_b	end for;end config;\end{lstlisting}\vspace{1cm}8位数码管扫描模块\footnote{加入此模块和7段译码器目的在于在8位数码管上同步观察输入信号，同时在检测到目标序列后点亮LED灯。}：\begin{lstlisting}[language=VHDL]--generate 1 in 8 mux code and selected signallibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity MUX8_1SCAN is	port(clkscan:in std_logic;		din:in std_logic_vector(31 downto 0);		dout:out std_logic_vector(3 downto 0);		sel:out std_logic_vector(2 downto 0)	);end MUX8_1SCAN;architecture behav of MUX8_1SCAN is	signal count:std_logic_vector(2 downto 0);begin	process(clkscan)	begin		if clkscan'event and clkscan='1' then			--loop:000->001->...->111			if count="111" then				count<="000";			else count<=count+1;			end if;		end if;	end process;	process(count,din)	begin		case count is			--mapping			when "000" =>dout<=din(3 downto 0);			when "001" =>dout<=din(7 downto 4);			when "010" =>dout<=din(11 downto 8);			when "011" =>dout<=din(15 downto 12);			when "100" =>dout<=din(19 downto 16);			when "101" =>dout<=din(23 downto 20);			when "110" =>dout<=din(27 downto 24);			when others =>dout<=din(31 downto 28);		end case;	end process;	--output the sel signal	sel<=count;end behav;\end{lstlisting}\vspace{1cm}BCD码到7段码译码模块：\begin{lstlisting}[language=VHDL]--convert 8421bcd code to led 7_segement codelibrary ieee;use ieee.std_logic_1164.all;entity BCD2LED is	port(digit:in std_logic_vector(3 downto 0);		   led:out std_logic_vector(6 downto 0));end BCD2LED;architecture behav of BCD2LED isbegin	process(digit)	begin		case digit is			--mapping			when "0000" =>led<="0111111";			when "0001" =>led<="0000110";			when "0010" =>led<="1011011";			when "0011" =>led<="1001111";			when "0100" =>led<="1100110";			when "0101" =>led<="1101101";			when "0110" =>led<="1111101";			when "0111" =>led<="0000111";			when "1000" =>led<="1111111";			when others =>led<="1101111";		end case;	end process;end behav;	\end{lstlisting}\vspace{1cm}\subsection[\textbf{顶层文件}]{\textbf{进行元件例化}}在顶层文件中进行RTL描述，例化底层元件：\begin{lstlisting}[language=VHDL]--RTL Top-level entitylibrary ieee;use ieee.std_logic_1164.all;entity toplevel is	port(clkin,clr:in std_logic;			clkon:in std_logic;			sel:out std_logic_vector(2 downto 0);			led:out std_logic;    led7:out std_logic_vector(6 downto 0));end toplevel;architecture rtl of toplevel is	--seqgen.vhd	component seqgen is		port(clkin:in std_logic;	       clr:in std_logic;	       sqn:out std_logic);	end component;	--sqndtc.vhd	component sqndtc is		port(clkin:in std_logic;		   clr:in std_logic;		   din:in std_logic;		   dset:in std_logic_vector(7 downto 0);			led:out std_logic;		     d:out std_logic_vector(31 downto 0));	end component;	--8mux1.vhd	component MUX8_1SCAN is		port(clkscan:in std_logic;		din:in std_logic_vector(31 downto 0);		dout:out std_logic_vector(3 downto 0);		sel:out std_logic_vector(2 downto 0)	);	end component;	--bcd2led.vhd	component BCD2LED is		port(digit:in std_logic_vector(3 downto 0);		   led:out std_logic_vector(6 downto 0));	end component;	signal sqn,tmpled:std_logic;	signal sqnset:std_logic_vector(7 downto 0);	signal ledtmp:std_logic_vector(31 downto 0);	signal dout:std_logic_vector(3 downto 0);begin	sqnset <="10001110";	unit_sqngen:seqgen port map(clkin,clr,sqn);	unit_sqndtc:sqndtc port map(clkin,clr,sqn,sqnset,led,ledtmp);	unit_MUX8_1SCAN :MUX8_1SCAN port map(clkon,ledtmp,dout,sel);	unit_BCD2LED:BCD2LED port map(dout,led7);end rtl;\end{lstlisting}\subsection{\textbf{编译仿真}}选择``Processing''->``Start Compilation''，编译无误。设置完成输入波形后再``Processing''->``Start Simulation''进行仿真。\section{\textbf{实验结果}}仿真结果如下，在实验箱上跑的结果也正确，但是因为led点亮时间太短，对摄影技术有较硬要求，故没有成功拍照。\begin{figure}[htbp]\centering\includegraphics[scale=0.6]{simu.eps}\caption{\small{仿真结果}}\end{figure}\section{\textbf{心得体会}}\subsection{\textbf{总结与收获}}\begin{enumerate}\item[1.]巩固了QuartusII环境下用VHDL进行设计的基本方法；\item[2.]巩固了QuartusII集成开发环境的使用和设计流程；\item[3.]巩固了用VHDL进行层次化设计的基本方法；\item[4.]巩固了EDA实验箱的基本功能,巩固了管脚映射，硬件编程下载的方法；\item[5.]巩固了序列发生器，检测器和状态机的设计原理。\end{enumerate}\begin{thebibliography}{9}\bibitem{DDPP}	John F. Wakerly,	\emph{Digital Design Principles and Practices}.	Prentice Hall,	2005.\bibitem{eda}	谭会生\quad 张昌凡,	\emph{EDA技术及应用}.	西安电子科技大学出版社,	2004.\end{thebibliography}\end{document}